[ 921CGELDICP13 ] PR Design of Integrated Circuits

(*) Leider ist diese Information in Deutsch nicht verfügbar.
Workload Ausbildungslevel Studienfachbereich VerantwortlicheR Semesterstunden Anbietende Uni
3 ECTS M - Master Informatik Dieter Ehrenstorfer 2 SSt Johannes Kepler Universität Linz
Quellcurriculum Masterstudium Computer Science 2013W
Ziele (*)Students will learn the hardware description language VHDL and they should be able to realise simple hardware designs for FPGA-based systems afterwards. Furthermore they should be able to verify digital circuits by the means of simulation and to synthesise a design for a target FPGA technology at the end of this lecture.
In the course exercises will be used to apply the theoretical knowledge to practical problems that will be assembled to a more complex application in small incremental steps. A key focus is set onto the practical work and the tailoring of a complex problem to solvable subsets.
Lehrinhalte (*)The lecture provides theoretical input combined with practical work and application of the theory. The following topics will be held:
* Syntax of VHDL in general

  • Simulation cycle and related features
  • Special data types and type conversions for direct arithmetic operations
  • Special descriptive approaches to generate VHDL-code for synthesis
  • Creation of effective test-benches
  • Comparison between VHDL description and generated hardware
  • Integration of FPGA-based RAM primitives into the design
  • Extraction of design parameters (possible clock frequency, etc.)
  • Dividing of complex tasks into small and testable subsets
Beurteilungskriterien (*)Marking is based on consecutive homework and a final project
Lehrmethoden (*)Blendend-learning approach with in-class theoretical inputs combined with online-resources.

Students are given assignments that have to be handed in electronically. A final project has to be presented in class at the end of the lecture
Abhaltungssprache English
Literatur (*)Electronic course material is made available for download via JKU moodle. There additional information and other references are available.
Lehrinhalte wechselnd? Nein
Äquivalenzen INMAWPREINS: PR Entwurf integrierter Schaltungen (3 ECTS)
Teilungsziffer 15
Zuteilungsverfahren Direktzuteilung